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Constrained optimization problems are at the heart of many decision, scheduling, error-correction and cyber security applications. Many constrained optimizations are NP-hard in nature, which makes solving them extremely resource demanding, either in terms of computation time or hardware components or energy. Given the importance of these problems, any improvements in efficiency in solving such problems are in great need. As an example, there is a world-wide competition taking place every two years, devoted to finding the best solvers for one of the representative NP-hard constrained optimization problems, i.e., Boolean Satisfiability (SAT).

Most of the efforts on improving solvers for constrained optimization problems aim at developing more effective search algorithms with the understanding that these algorithms would eventually be implemented on modern general-purpose digital computing platforms such as multi-core or many-core processors. Several researchers have investigated implementing such essentially digital algorithms on application specific integration circuits, hence achieving better performance, but at a higher cost. These approaches have been enjoying good success, as they readily benefit from the continuous improvements in CMOS technology that have been governed by Moore’s Law.

However, with Moore’s Law coming to an end, exploring novel computational paradigms (e.g., quantum computing and neuromorphic computing) is more imperative than ever. Recently there has been increased interest in designing analog, or mixed-signal solvers for some specific NP-hard optimization problems based on continuous–time dynamical systems. Furthermore, a number of researchers are investigating approaches that exploit intrinsic properties exhibited by certain beyond-CMOS devices to solve NP-hard optimization problems.

The purpose of this workshop is to bring together researchers who work on all these aspects employing various approaches for solving hard constraint satisfaction and optimization problems. The workshop will provide a forum for researchers to exchange ideas and discuss the challenges and opportunities in this area.

NSF has graciously provided limited travel support to participants who face travel budget difficulties. If you would like to apply for the travel support, please contact the organizers.

More details about participation and posters can be found at: https://naho.nd.edu/

SPONSORS

Dates & Location

June 13 – June 14, 2023

Morris Inn,
Notre Dame, IN

Organizers

X. Sharon Hu

Professor,
Department of Computer Science and Engineering,
University of Notre Dame

ZoltanZoltán Toroczkai

Professor,
Physics Department, Concurrent Professor, Department of Computer Science and Engineering,
University of Notre Dame

siddharthSiddharth Joshi

Assistant Professor,
Department of Computer Science and Engineering,
University of Notre Dame

SPONSORS